View UDA1341TS_333840.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
UDA1341TS Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
Product specification Supersedes data of 2001 Jun 29 2002 May 16
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.21.1 7.21.2 7.21.3 7.21.4 FEATURES General Multiple format data interface DAC digital sound processing Advanced audio configuration GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System clock Pin compatibility Analog front end Programmable Gain Amplifier (PGA) Analog-to-Digital Converter (ADC) Digital Automatic Gain Control (AGC) AGC status detection Digital mixer Decimation filter (ADC) Overload detection (ADC) Mute (ADC) Interpolation filter (DAC) Peak detector Quick mute Noise shaper (DAC) Filter Stream Digital-to-Analog Converter (FSDAC) Multiple format input/output interface L3-interface Address mode Data transfer mode Programming the sound processing and other features STATUS control DATA0 direct control DATA0 extended programming registers DATA1 control 15.2 15.3 15.4 15.5 16 17 18 8 9 10 11 12 13 14 15 15.1 LIMITING VALUES
UDA1341TS
THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS (ANALOG) AC CHARACTERISTICS (DIGITAL) APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2002 May 16
2
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
1 1.1 FEATURES General
UDA1341TS
* Low power consumption * 3.0 V power supply * 256fs, 384fs or 512fs system clock frequencies (fsys) * Small package size (SSOP28) * Partially pin compatible with UDA1340M and UDA1344TS * Fully integrated analog front end including digital AGC * ADC plus integrated high-pass filter to cancel DC offset * ADC supports 2 V (RMS value) input signals * Overload detector for easy record level control * Separate power control for ADC and DAC * No analog post filter required for DAC * Easy application * Functions controllable via L3-interface. 1.2 Multiple format data interface * Optional differential input configuration for enhanced ADC sound quality * Stereo line output (under microcontroller volume control) * Digital peak level detection * High linearity, dynamic range and low distortion. 2 GENERAL DESCRIPTION
* I2S-bus, MSB-justified and LSB-justified format compatible * Three combinational data formats with MSB data output and LSB 16, 18 or 20 bits data input * 1fs input and output format data rate. 1.3 DAC digital sound processing
The UDA1341TS is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. Its fully integrated analog front end, including Programmable Gain Amplifier (PGA) and a digital Automatic Gain Control (AGC). Digital Sound Processing (DSP) featuring makes the device an excellent choice for primary home stereo MiniDisc applications, but by virtue of its low power and low voltage characteristics it is also suitable for portable applications such as MD/CD boomboxes, notebook PCs and digital video cameras. The UDA1341TS is similar to the UDA1340M and the UDA1344TS but adds features such as digital mixing of two input signals and one channel with a PGA and a digital AGC. The UDA1341TS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits, the LSB-justified serial data format with word lengths of 16, 18 and 20 bits and three combinations of MSB data output combined with LSB 16, 18 and 20 bits data input. The UDA1341TS has DSP features in playback mode like de-emphasis, volume, bass boost, treble and soft mute, which can be controlled via the L3-interface with a microcontroller.
* Digital dB-linear volume control (low microcontroller load) * Digital tone control, bass boost and treble * Digital de-emphasis for 32, 44.1 or 48 kHz audio sample frequencies (fs) * Soft mute. 1.4 Advanced audio configuration
* DAC and ADC polarity control * Two channel stereo single-ended input configuration * Microphone input with on-board PGA 3 ORDERING INFORMATION TYPE NUMBER UDA1341TS
PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm VERSION SOT341-1
2002 May 16
3
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
4 QUICK REFERENCE DATA SYMBOL Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) IDDA(DAC) IDDD Tamb Vi(rms) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current digital supply current operating ambient temperature operation mode ADC power-down operation mode DAC power-down operation mode 2.4 2.4 2.4 - - - - - -20 notes 1 and 2 stand-alone mode 0 dB -60 dB; A-weighted double differential mode 0 dB -60 dB; A-weighted S/N signal-to-noise ratio Vi = 0 V; A-weighted stand-alone mode double differential mode cs channel separation Programmable gain amplifier (THD + N)/S total harmonic distortion-plus-noise to signal ratio 1 kHz; fs = 44.1 kHz 0 dB -60 dB; A-weighted S/N signal-to-noise ratio Vi = 0 V; A-weighted supply voltage = 3 V; note 3 0 dB -60 dB; A-weighted code = 0; A-weighted Digital-to-analog converter Vo(rms) (THD+N)/S S/N cs Notes output voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation - - - - - - - - - - - - - - - - PARAMETER CONDITIONS MIN.
UDA1341TS
TYP.
MAX.
UNIT
3.0 3.0 3.0 12.5 6.0 7.0 50 7.0 - 1.0 -85 -37 -90 -40 97 100 100
3.6 3.6 3.6 - - - - - +85 - -80 -33 -85 -36 - - -
V V V mA mA mA A mA C V dB dB dB dB dB dB dB
Analog-to-digital converter input voltage (RMS value) (THD + N)/S total harmonic distortion-plus-noise to signal ratio
-85 -37 95
- - - - -86 - - -
dB dB dB
900 -91 -40 100 100
mV dB dB dB dB
1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 k is used in series with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS). 2. The ADC input signal scales inversely proportional with the power supply voltage. 3. The DAC output voltage scales linear with the DAC analog supply voltage.
2002 May 16
4
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
5 BLOCK DIAGRAM
UDA1341TS
handbook, full pagewidth
VDDA(ADC) 3 6
VSSA(ADC) 1
VDDD 10
VSSD 11
VADCP 7
VADCN 5 8
VINL2
VINR2
PGA ADC2 VINL1 2 0 dB/6 dB SWITCH ADC1 ADC2
PGA 0 dB/6 dB SWITCH ADC1 22 4 VINR1
UDA1341TS
DIGITAL AGC
AGCSTAT
DIGITAL MIXER 9
DECIMATION FILTER 18 16 17 19 DIGITAL INTERFACE L3-BUS INTERFACE
OVERFL
DATAO BCK WS DATAI
13 14 15
L3MODE L3CLOCK L3DATA
DSP FEATURES
12
SYSCLK
QMUTE
23
INTERPOLATION FILTER
PEAK DETECTOR 20 21
NOISE SHAPER Vref 28
TEST1 TEST2
DAC VOUTL 26
DAC 24 VOUTR
25 VDDA(DAC)
27 VSSA(DAC)
MGR427
Fig.1 Block diagram.
2002 May 16
5
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
6 PINNING SYMBOL VSSA(ADC) VINL1 VDDA(ADC) VINR1 VADCN VINL2 VADCP VINR2 OVERFL VDDD VSSD SYSCLK L3MODE L3CLOCK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DESCRIPTION ADC analog ground ADC1 input left ADC analog supply voltage ADC1 input right ADC negative reference voltage ADC2 input left ADC positive reference voltage ADC2 input right decimation filter overflow output digital supply voltage digital ground system clock 256fs, 384fs or 512fs L3-bus mode input L3-bus clock input SYMBOL L3DATA BCK WS DATAO DATAI TEST1 TEST2 AGCSTAT QMUTE VOUTR VDDA(DAC) VOUTL VSSA(DAC) Vref PIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28
UDA1341TS
DESCRIPTION L3-bus data input and output bit clock input word select input data output data input test control 1 (pull-down) test control 2 (pull-down) AGC status quick mute input DAC output right DAC analog supply voltage DAC output left DAC analog ground ADC and DAC reference voltage
handbook, halfpage
VSSA(ADC) 1 VINL1 2
28 Vref 27 VSSA(DAC) 26 VOUTL 25 VDDA(DAC) 24 VOUTR 23 QMUTE 22 AGCSTAT
handbook, halfpage
VSSA(ADC) 1 VINL1 2
28 Vref 27 VSSA(DAC) 26 VOUTL 25 VDDA(DAC) 24 VOUTR 23 QMUTE 22 AGCSTAT
VDDA(ADC) 3 VINR1 4 VADCN 5 VINL2 6 VADCP 7
VDDA(ADC) 3 VINR1 4 VADCN 5 VINL2 6 VADCP 7
UDA1341TS
VINR2 8 OVERFL 9 VDDD 10 VSSD 11 SYSCLK 12 L3MODE 13 L3CLOCK 14
MGR428
UDA1341TS
21 TEST2 20 TEST1 19 DATAI 18 DATAO 17 WS 16 BCK 15 L3DATA VINR2 8 OVERFL 9 VDDD 10 VSSD 11 SYSCLK 12 L3MODE 13 L3CLOCK 14
MGR429
21 TEST2 20 TEST1 19 DATAI 18 DATAO 17 WS 16 BCK 15 L3DATA
Marked pins are compatible with UDA1340M
Fig.2 Pin configuration.
Fig.3 Compatible pins with UDA1340M.
2002 May 16
6
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7 7.1 FUNCTIONAL DESCRIPTION System clock 7.5
UDA1341TS
Analog-to-Digital Converter (ADC)
The UDA1341TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256fs, 384fs or 512fs. The system clock must be locked in frequency to the digital interface signals. 7.2 Pin compatibility
The stereo ADC of the UDA1341TS consists of two 3rd-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128. 7.6 Digital Automatic Gain Control (AGC)
The UDA1341TS is partially pin compatible with the UDA1340M and UDA1344TS, making an upgrade of a printed-circuit board from UDA1340M to UDA1341TS easier. The pins that are compatible with the UDA1340M are marked in Fig.3. 7.3 Analog front end
The analog front end of the UDA1341TS consists of two stereo ADCs with a Programmable Gain Amplifier (PGA) in channel 2. The PGA is intended to pre-amplify a microphone signal applied to the input channel 2. Input channel 1 has a selectable 0 or 6 dB gain stage, to be controlled via the L3-interface. In this way, input signals of 1 V (RMS value) or 2 V (RMS value) e.g. from a CD source can be supported using an external resistor of 12 k in series with the input channel 1. The application modes are given in Table 1. Table 1 Application modes using input gain stage INPUT GAIN SWITCH 0 dB 6 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS value) input signal; note 1 1 V (RMS value) input signal 1 V (RMS value) input signal 0.5 V (RMS value) input signal
Input channel 2 has a digital AGC to compress the dynamic range when a microphone signal is applied to input channel 2. The digital AGC can be switched on and off via the L3-interface. In the on state the AGC compresses the dynamic range of the input signal of input channel 2. Via the L3-interface the user can set the parameters of the AGC: attack time, decay time and output level. When the AGC is set off via the L3-interface, the gain of input channel 2 can be set manually. In this case the gain of the PGA and digital AGC are combined. The range of the gain of the input channel 2 is from -3 to +60.5 dB in steps of 0.5 dB. 7.7 AGC status detection
The AGCSTAT signal from the digital AGC is HIGH when the gain level of the AGC is below 8 dB. This signal can be used to give the PGA a new gain setting via the L3-interface and to power e.g. a LED. 7.8 Digital mixer
The two stereo ADCs (including the AGC) can be used in four modes: * ADC1 only mode (for line input); input channel 2 is off * ADC2 only mode, including PGA and digital AGC (for microphone input); input channel 1 is off * ADC1 + ADC2 mixer mode, including PGA and AGC * ADC1 and ADC2 double differential mode (improved ADC performance). Important: In order to prevent crosstalk between the line inputs no signal should be applied to the microphone input in the double differential mode. In all modes (except the double differential mode) a reference voltage is always present at the input of the ADC. However, in the double differential mode there is no reference voltage present at the microphone input. In the mixer mode, the output signals of both ADCs in channel 1 and channel 2 (after the digital AGC) can be mixed with coefficients that can be set via the L3-interface. The range of the mixer coefficients is from 0 to - dB in 1.5 dB steps.
RESISTOR (12 k) Present Present Absent Absent Note
1. If there is no need for 2 V (RMS value) input signal support, the external resistor should not be used. 7.4 Programmable Gain Amplifier (PGA)
The PGA can be set via the L3-interface at the gain settings: -3, 0, 3, 9, 15, 21 or 27 dB.
2002 May 16
7
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.9 Decimation filter (ADC) 7.12 Interpolation filter (DAC)
UDA1341TS
The decimation from 128fs is performed in two stages. sin x The first stage realizes 3rd order ----------- characteristic, x decimating by 16. The second stage consists of 3 half-band filters, each decimating by a factor of 2. Table 2 Decimation filter characteristics ITEM Passband ripple Stop band Dynamic range Overall gain CONDITIONS 0 to 0.45fs >0.55fs 0 to 0.45fs input channel 1; 0 dB input VALUE (dB) 0.05 -60 108 -1.16
The digital filter interpolates from 1fs to 128fs by means of a cascade of a recursive filter and a Finite Impulse Response (FIR) filter. Table 3 Interpolation filter characteristics ITEM Passband ripple Stop band Dynamic range 7.13 Peak detector CONDITIONS 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.03 -50 108
7.10
Overload detection (ADC)
This name is convenient but a little inaccurate. In practice the output is used to indicate whenever that output data, in either the left or right channel, is bigger than -1 dB (actual figure is -1.16 dB) of the maximum possible digital swing. If this condition is detected the OVERFL output is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. 7.11 Mute (ADC)
In the playback path a peak level detector is build in. The position of the peak detection can be set via the L3-interface to either before or after the sound features. The peak level detector is implemented as a peak-hold detector, which means that the highest sound level is hold until the peak level is read out via the L3-interface. After read-out the peak level registers are reset. 7.14 Quick mute
A hard mute can be activated via the static pin QMUTE. When QMUTE is set HIGH, the output signal is instantly muted to zero. Setting QMUTE to LOW, the mute is instantly de-activated. 7.15 Noise shaper (DAC)
On recovery from power-down or switching on of the system clock, the serial data output on pin DATAO is held at LOW level until valid data is available from the decimation filter. This time depends on whether the DC-cancellation filter is selected: * DC cancel off: 1024 t = ------------ ; t = 23.2 ms at fs = 44.1 kHz fs * DC cancel on: 12288 t = --------------- ; t = 279 ms at fs = 44.1 kHz. fs
The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique allows for high signal-to-noise ratios. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter.
2002 May 16
8
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.16 Filter Stream Digital-to-Analog Converter (FSDAC) 7.17
UDA1341TS
Multiple format input/output interface
The UDA1341TS supports the following data formats: * I2S-bus with word length up to 20 bits * MSB-justified serial format with word length up to 20 bits * LSB-justified serial format with word length of 16, 18 or 20 bits * MSB data output with LSB 16, 18 or 20 bits input. Left and right data-channel words are time multiplexed. The formats are illustrated in Fig.4. The UDA1341TS allows for double speed data monitoring purposes. In this case the sound features bass boost, treble and de-emphasis cannot be used. However, volume control and soft-mute can still be controlled. The double speed monitoring option can be set via the L3-interface. The bit clock frequency must be 64 times word select frequency or less, so fBCK 64 x fWS.
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.
2002 May 16
9
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
andbook, full pagewidth
2002 May 16 10
Philips Semiconductors
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
WS 1 BCK DATA MSB 2
LEFT 3 >=8 1 2
RIGHT 3
>=8
B2
LSB MSB
B2 INPUT FORMAT I2S-BUS
LSB MSB
WS 1 BCK DATA MSB B2 2
LEFT 3 >=8 1 2
RIGHT 3 >=8
LSB MSB
B2
LSB MSB MSB-JUSTIFIED FORMAT
B2
WS
LEFT 16 15 2 1
RIGHT 16 15 2 1
BCK DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB
WS
LEFT 18 17 16 15 2 1 18
RIGHT 17 16 15 2 1
BCK DATA MSB B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS 20 BCK DATA MSB B2 19
LEFT 18 17 16 15 2 1 20 19 18
RIGHT 17 16 15 2 1
UDA1341TS
Product specification
B3
B4
B5
B6
B19
LSB
MSB
B2
B3
B4
B5
B6
B19
LSB
MGG841
LSB-JUSTIFIED FORMAT 20 BITS
Fig.4 Serial interface formats.
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.18 L3-interface
UDA1341TS
The UDA1341TS has a microcontroller input mode. In the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: * Reset * System clock frequency * Power control * DAC gain switch * ADC input gain switch * ADC/DAC polarity control * Double speed playback * De-emphasis * Volume * Mode switch * Bass boost * Treble * Mute * MIC sensitivity control * AGC control * Input amplifier gain control * Digital mixer control * Peak detection position. Via the L3-interface the peak level value of the signal in the DAC path can be read out from the UDA1341TS to the microcontroller. The exchange of data and control information between the microcontroller and the UDA1341TS is accomplished through a serial hardware L3-interface comprising the following pins: * L3DATA: microcontroller interface data line * L3MODE: microcontroller interface mode line * L3CLOCK: microcontroller interface clock line. Information transfer through the microcontroller bus is organized in accordance with the so called `L3' format, in which two different modes of operation can be distinguished: address mode and data transfer mode.
The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer can be in both directions: input to the UDA1341TS to program its sound processing and system controlling features and output from the UDA1341TS to provide the peak level value. 7.19 Address mode
The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.5. Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1341TS is 000101. Data bits 0 to 1 indicate the type of the subsequent data transfer as shown in Table 4. In the event that the UDA1341TS receives a different address, it will deselect its microcontroller interface logic. 7.20 Data transfer mode
The selection activated in the address mode remains active during subsequent data transfers, until the UDA1341TS receives a new address command. The fundamental timing of data transfers is essentially the same as the timing in the address mode and is given in Fig.6. Note that `L3DATA write' denotes data transfer from the microcontroller to the UDA1341TS and `L3DATA peak read' denotes data transfer in the opposite direction. The maximum input clock and data rate is 64fs. All transfers are byte-wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1341TS after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.7.
2002 May 16
11
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
Table 4 Selection of data transfer MODE DATA0 TRANSFER
UDA1341TS
BIT 1 BIT 0 0 0
direct addressing registers: volume, bass boost, treble, peak detection position, de-emphasis, mute and mode extended addressing registers: digital mixer control, AGC control, MIC sensitivity control, input gain, AGC time constant and AGC output level
0 1 1
1 0 1
DATA1
peak level value read-out (information from UDA1341TS to microcontroller)
STATUS reset, system clock frequency, data input format, DC-filter, input gain switch, output gain switch, polarity control, double speed and power control not used
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGR431
Fig.5 Timing address mode.
2002 May 16
12
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
UDA1341TS
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
th(L3)DA
tsu(L3)DA
th(L3)DA
L3DATA write
BIT 0
BIT 7
L3DATA read
PL0
PL1
PL2
PL3
PL4
PL5
MGR430
Fig.6 Timing for data transfer mode.
handbook, full pagewidth
tstp(L3)
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGR432
Fig.7 Multibyte transfer.
2002 May 16
13
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21 Programming the sound processing and other features * DATA0
UDA1341TS
The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 0 and bit 1 (see Table 4). The second selection is performed by the 2 or 3 MSBs of the data byte (bits 7 and 6 or bits 7, 6 and 5). The other bits in the data byte (bits 5 to 0 or bits 4 to 0) represent the value that is placed in the selected registers. For the UDA1341TS the following modes can be selected: * STATUS In this mode the features reset, system clock frequency, data input format, DC-filter, input gain switch, output gain switch, polarity control, double speed and power control can be controlled. Table 5 Default settings FEATURE
There are two addressing modes: direct addressing mode and extended addressing mode. Direct addressing mode is using the 2 MSB bits of the data byte. Via this addressing mode the features volume, bass boost, treble, peak position, de-emphasis, mute, and mode can be controlled directly. Extended addressing mode is provided for controlling the features digital mixer, AGC control, MIC sensitivity, input gain, AGC time constants, and AGC output level. An extended address can be set via the EA registers (3 bits). The data in the extended registers can be set by writing data to the ED registers (5 bits). * DATA1 In this mode the detected peak level value can be read out.
SYMBOL Status OGS IGS PAD PDA DS PC Output gain switch Input gain switch Polarity of ADC Polarity of DAC Double speed
SETTING OR VALUE
0 dB 0 dB non-inverting non-inverting single speed on
Power control ADC and DAC
Direct control VC BB TR PP DE MT M Volume control Bass boost Treble Peak detection position De-emphasis Mute Mode switch 0 dB 0 dB 0 dB after the tone features no de-emphasis no mute flat -6 dB -6 dB 0 dB double differential disable AGC 11 ms and100 ms -9 dB FS 14
Extended programming MA MB MS MM AG AT AL 2002 May 16 Mixer gain channel 1 Mixer gain channel 2 MIC sensitivity Mixer mode switch AGC control AGC attack and decay time AGC output level
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21.1 Table 6 STATUS CONTROL Data transfer of type `STATUS'
UDA1341TS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 RST SC1 SC0 IF2 IF1 IF0 DC RST = reset
REGISTER SELECTED SC = system clock frequency (2 bits) IF = data input format (3 bits) DC = DC-filter
1
OGS
IGS
PAD
PDA
DS
PC1
PC0
OGS = output gain (6 dB) switch IGS = input gain (6 dB) switch PAD = polarity of ADC PDA = polarity of DAC DS = double speed PC = power control (2 bits)
7.21.1.1
Reset
7.21.1.4
Data input format
A 1-bit value to initialize the L3-registers with the default settings except system clock frequency. Table 7 RST 0 1 no reset reset Reset settings FUNCTION
A 3-bit value to select the data input format. Table 10 Data input format settings IF2 IF1 IF0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I2S-bus LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits MSB-justified LSB-justified 16 bits input and MSB-justified output LSB-justified 18 bits input and MSB-justified output LSB-justified 20 bits input and MSB-justified output FUNCTION
7.21.1.2
System clock frequency
A 2-bit value to select the used external clock frequency. Table 8 System clock settings FUNCTION 512fs 384fs 256fs not used
SC1 SC0 0 0 1 1 0 1 0 1
7.21.1.3
DC-filter
A 1-bit value to enable the digital DC-filter. Table 9 DC 0 1 no DC-filtering DC-filtering DC-filtering settings FUNCTION
2002 May 16
15
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21.1.5 Output gain switch 7.21.1.9 Double speed
UDA1341TS
A 1-bit value to control the DAC output gain switch. The default setting is given in Table 5. Table 11 Gain switch of DAC settings OGS 0 1 GAIN OF DAC 0 dB 6 dB
A 1-bit value to enable the double speed playback. The default setting is given in Table 5. Table 15 Double speed settings DS 0 1 FUNCTION single speed playback double speed playback
7.21.1.6
Input gain switch
7.21.1.10 Power control
A 2-bit value to disable the ADC and/or DAC to reduce power consumption. The default setting is given in Table 5. Table 16 Power control settings FUNCTION PC1 0 PC0 ADC 0 1 0 1 off off on on 0 1 1 DAC off on off on
A 1-bit value to control the ADC input gain switch. The default setting is given in Table 5. Table 12 Gain switch of ADC settings IGS 0 1 GAIN OF ADC 0 dB 6 dB
7.21.1.7
Polarity of ADC
A 1-bit value to control the ADC polarity. The default setting is given in Table 5. Table 13 Polarity control of ADC settings PAD 0 1 non-inverting inverting POLARITY OF ADC
7.21.1.8
Polarity of DAC
A 1-bit value to control the DAC polarity. The default setting is given in Table 5. Table 14 Polarity control of DAC settings PDA 0 1 non-inverting inverting POLARITY OF DAC
2002 May 16
16
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21.2 DATA0 DIRECT CONTROL
UDA1341TS
Table 17 Data transfer of type `DATA0' BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 1 0 1 0 VC5 BB3 PP VC4 BB2 DE1 VC3 BB1 DE0 VC2 BB0 MT VC1 TR1 M1 VC0 TR0 M0 REGISTER SELECTED VC = volume control (6 bits) BB = bass boost (4 bits) TR = treble (2 bits) PP = peak detection position DE = de-emphasis (2 bits) MT = mute M = mode switch (2 bits) 1 1 1 1 0 1 0 ED4 0 ED3 EA2 ED2 EA1 ED1 EA0 ED0 EA = extended address (3 bits) ED = extended data (5 bits)
7.21.2.1
Volume control
7.21.2.2
Bass boost
A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to - dB in steps of 1 dB. The default setting is given in Table 5. Table 18 Volume settings VC5 0 0 0 0 : 1 1 1 1 1 VC4 0 0 0 0 : 1 1 1 1 1 VC3 0 0 0 0 : 1 1 1 1 1 VC2 0 0 0 0 : 0 1 1 1 1 VC1 0 0 1 1 : 1 0 0 1 1 VC0 0 1 0 1 : 1 0 1 0 1 VOLUME (dB) 0 0 -1 -2 : -58 -59 -60 - -
A 4-bit value to program the bass boost settings. The used set depends on the mode bits. The default setting is given in Table 5. Table 19 Bass boost settings BASS BOOST BB3 BB2 BB1 BB0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 FLAT (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. (dB) 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 MAX. (dB) 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24
2002 May 16
17
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21.2.3 Treble 7.21.2.6 Mute
UDA1341TS
A 2-bit value to program the treble setting. The used set depends on the mode bits. The default setting is given in Table 5. Table 20 Treble settings TREBLE TR1 0 0 1 1 TR0 0 1 0 1 FLAT (dB) 0 0 0 0 MIN. (dB) 0 2 4 6 MAX. (dB) 0 2 4 6
A 1-bit value to enable the digital mute. The default setting is given in Table 5. Table 23 Mute settings MT 0 1 no mute mute FUNCTION
7.21.2.7
Mode
A 2-bit value to program the mode of the sound processing filters of bass boost and treble. The default setting is given in Table 5. Table 24 Mode filter switch settings M1 0 0 1 1 M0 0 1 0 1 flat minimum minimum maximum FUNCTION
7.21.2.4
Peak detection position
A 1-bit value to control the position of the peak level detector in the signal processing path. The default setting is given in Table 5. Table 21 Peak detection position settings PP 0 1 FUNCTION before tone features after tone features
7.21.2.5
De-emphasis
A 2-bit value to enable the digital de-emphasis filter. The default setting is given in Table 5. Table 22 De-emphasis settings DE1 0 0 1 1 DE0 0 1 0 1 FUNCTION no de-emphasis de-emphasis: 32 kHz de-emphasis: 44.1 kHz de-emphasis: 48 kHz
2002 May 16
18
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21.3 DATA0 EXTENDED PROGRAMMING REGISTERS
UDA1341TS
Table 25 Extended control registers EA2 0 0 0 1 1 1 EA1 0 0 1 0 0 1 EA0 0 1 0 0 1 0 ED4 ED3 ED2 ED1 ED0 REGISTER SELECTED
MA4 MA3 MA2 MA1 MA0 MA = mixer gain channel 1 (5 bits) MB4 MB3 MB2 MB1 MB0 MB = mixer gain channel 2 (5 bits) MS2 MS1 MS0 MM1 MM0 MS = MIC sensitivity (3 bits) MM = mixer mode (2 bits) AG IG6 AT2 0 IG5 AT1 0 IG4 AT0 IG1 IG3 AL1 IG0 IG2 AG = AGC control IG = input amplifier gain channel 2 (2 bits) IG = input amplifier gain channel 2 (5 bits) AL = AGC output level (2 bits) AL0 AT = AGC time constant (3 bits)
Programming via extended addressing is done by first sending a DATA0 data byte EA (3 bits) which specifies the addresses of the extended register followed by a DATA0 data byte which specifies the contents of the extended data register (5 bits). The EA extended addresses and names of the extended data registers are given in Table 25.
7.21.3.2
MIC sensitivity
A 3-bit value to program eight gain settings of the microphone amplifier. These settings are valid only when AGC control is enabled and not in the double differential mode. The default setting is given in Table 5. Table 27 MIC sensitivity settings MS2 MS1 MS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MIC AMPLIFIER GAIN (dB) -3 0 +3 +9 +15 +21 +27 not used
7.21.3.1
Mixer gain control
Two 5-bit values to program the channel 1 (MA) and channel 2 (MB) coefficients in the mixer mode. The range is from 0 to - dB in steps of 1.5 dB. The default settings are given in Table 5. Table 26 Mixer gain control channel 1 and channel 2 settings MA4 MA3 MA2 MA1 MA0 MB4 MB3 MB2 MB1 MB0 0 0 0 : 1 1 1 0 0 0 : 1 1 1 0 0 0 : 1 1 1 0 0 1 : 0 1 1 0 1 0 : 1 0 1 MIXER GAIN (dB) 0 -1.5 -3.0 : -43.5 -45.0 -
2002 May 16
19
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21.3.3 Mixer mode 7.21.3.6
UDA1341TS
Input channel 2 amplifier gain
A 2-bit value to program the mode of the digital mixer. There are four modes: double differential, input channel 1 select, input channel 2 select and digital mixer mode. The default setting is given in Table 5. Table 28 Mixer mode switch settings MM1 MM0 0 0 1 1 0 1 0 1 FUNCTION double differential mode input channel 1 select (input channel 2 off) input channel 2 select (input channel 1 off) digital mixer mode (input 1 x MA + input 2 x MB)
A 7-bit value to program the input channel 2 amplifier gain. The range is from -3 to +60.5 dB in steps of 0.5 dB. These settings are only valid when AGC control is disabled and not valid in the double differential mode. Table 31 Input channel 2 amplifier gain settings INPUT CHANNEL 2 AMPLIFIER GAIN (dB) -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 : 59.5 60.0 60.5
IG6 IG5 IG4 IG3 IG2 IG1 IG0
0 0 0 0 0 0 0 : 1 1 1
0 0 0 0 0 0 0 : 1 1 1
0 0 0 0 0 0 0 : 1 1 1
0 0 0 0 0 0 0 : 1 1 1
0 0 0 0 1 1 1 : 1 1 1
0 0 1 1 0 0 1 : 0 1 1
0 1 0 1 0 1 0 : 1 0 1
7.21.3.4
AGC control
A 1-bit value to enable the AGC input. The default setting is given in Table 5. Table 29 AGC control settings AG 0 1 FUNCTION disable AGC: manual gain setting through IG (7 bits) enable AGC: gain control with manual MIC sensitivity setting
7.21.3.7 7.21.3.5 AGC output level
A 2-bit value to program the AGC output level. The default setting is given in Table 5. Table 30 AGC output level settings AL1 0 0 1 1 AL0 0 1 0 1 OUTPUT LEVEL (dB FS) -9.0 -11.5 -15.0 -17.5
AGC time constant
A 3-bit value to program the attack and the decay parameters of the digital AGC. The default setting is given in Table 5. Table 32 AGC time constant settings AT2 0 0 0 0 1 1 1 1 AT1 0 0 1 1 0 0 1 1 AT0 0 1 0 1 0 1 0 1 ATTACK TIME (ms) 11 16 11 16 21 11 16 21 DECAY TIME (ms) 100 100 200 200 200 400 400 400
2002 May 16
20
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
7.21.4 DATA1 CONTROL
UDA1341TS
Table 33 Data transfer of type `DATA1' BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PL5 PL4 PL3 PL2 PL1 PL0 peak level value (6 bits) READ-OUT DATA
7.21.4.1
Peak level value
A 6-bit value to indicate the peak level value of the playback data. The largest value of the left and right channel data in the playback signal path is held since the last read-out of the microcontroller. Table 34 Peak level read-out data PL5 0 0 0 0 0 0 0 0 : 0 0 : 1 1 1 Notes 1. Peak value (dB) = (Peak level - 63.5) x 5 x log 2. 11 x log 2 2. For peak data >010011, the error in the peak value is < ------------------------4 3. For peak data <010100, the error is larger due to limited bit length. PL4 0 0 0 0 0 0 0 0 : 1 1 : 1 1 1 PL3 0 0 0 0 0 0 0 0 : 0 0 : 1 1 1 PL2 0 0 0 0 1 1 1 1 : 0 1 : 1 1 1 PL1 0 0 1 1 0 0 1 1 : 1 0 : 0 1 1 PL0 0 1 0 1 0 1 0 1 : 1 0 : 1 0 1 - n.a. n.a. -90.31 n.a. n.a. n.a. -84.29 : note 2 note 3 : -2.87 -1.48 0.00 PEAK VALUE(1) (dB)
2002 May 16
21
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
UDA1341TS
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); VDDD = VDDA = 3 V; all voltages measured with respect to ground; Tamb = 25 C; unless otherwise specified. SYMBOL VDD Txtal(max) Tstg Tamb Ves Ilu(prot) Isc(DAC) PARAMETER supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling latch-up protection current DAC short-circuit current: output short-circuited to VSSA(DAC) output short-circuited to VDDA(DAC) Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. 4. DAC operation cannot be guaranteed after a short-circuit has occurred. 9 THERMAL CHARACTERISTICS PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 90 UNIT K/W note 2 note 3 Tamb = 125 C; VDD = 3.6 V Tamb = 0 C; VDD = 3.0 V; note 4 note 1 CONDITIONS - - -65 -20 -2000 -250 - - - MIN. MAX. 5.0 150 +125 +85 +2000 +250 200 482 346 V C C C V V mA mA mA UNIT
SYMBOL Rth(j-a)
10 DC CHARACTERISTICS VDDD = VDDA = 3 V; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. SYMBOL Supplies VDDA(ADC) ADC analog supply voltage VDDA(DAC) VDDD IDDA(ADC) IDDA(DAC) IDDD DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current digital supply current note 1 note 1 note 1 operation mode ADC power-down operation mode DAC power-down operation mode DAC power-down ADC power-down 2.4 2.4 2.4 - - - - - - - 3.0 3.0 3.0 12.5 6.0 7.0 50 7.0 4.0 3.0 3.6 3.6 3.6 - - - - - - - V V V mA mA mA A mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 May 16
22
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
SYMBOL Digital input pins VIH VIL |ILI| Ci VOH VOL VADCP VADCN Ro(ref) Ri HIGH-level input voltage LOW-level input voltage input leakage current input capacitance IOH = -2 mA IOL = 2 mA 0.8VDDD -0.5 - - - - - - PARAMETER CONDITIONS MIN. TYP.
UDA1341TS
MAX.
UNIT
VDDD + 0.5 V 0.2VDDD 10 10 - 0.4 - 0.0 - - - - - - 3.0 - - 50 V A pF
Digital output pins HIGH-level output voltage LOW-level output voltage 0.85VDDD - - - 0.0 pin 28 measured at 1 kHz stand-alone mode double differential mode Ci Ri input capacitance Programmable gain amplifier (input channel 2) input resistance microphone mode double differential mode Digital-to-analog converter Ro Io(max) RL CL Vref Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads (above 50 pF) must be driven then a resistor of 100 must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. output resistance maximum output current load resistance load capacitance note 2 (THD + N)/S < 0.1% - - 3 - 0.13 0.22 - - - - 12.5 >1 k M - - - 12.5 6.25 20 k k pF - - VDDA 0.0 24 V V
Analog-to-digital converter positive reference voltage negative reference voltage Vref reference output resistance input resistance V V k
mA k pF
Reference voltage reference voltage with respect to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V
2002 May 16
23
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
UDA1341TS
11 AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3 V; fi = 1 kHz; fs = 44.1 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS - - stand-alone mode 0 dB -60 dB; A-weighted double differential mode 0 dB -60 dB; A-weighted S/N signal-to-noise ratio Vi = 0 V; A-weighted stand-alone mode double differential mode - - - - 97 100 100 30 - - - - dB dB dB dB - - -90 -40 -85 -36 dB dB - - -85 -37 -80 -33 dB dB MIN. TYP. - - MAX. UNIT
Analog-to-digital converter Vi(rms) input voltage (RMS value) unbalance between channels total harmonic distortion-plus-noise to signal ratio notes 1 and 2 1.0 0.1 V dB
Vi
(THD + N)/S
cs
PSRR
channel separation power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 30 mV minimum gain maximum gain digital gain step
Manual gain mode (AGC disabled) Gmin Gmax Gstep Vi(rms) - - - at full-scale -3 dB setting 0 dB setting 3 dB setting 9 dB setting 15 dB setting 21 dB setting 27 dB setting (THD + N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB -3 dB setting 0 dB setting 3 dB setting 9 dB setting 15 dB setting 21 dB setting 27 dB setting - - - - - - - -75 -85 -85 -85 -80 -75 -75 - - - - - - - dB dB dB dB dB dB dB - - - - - - - 1414 1000 708 355 178 89 44 - - - - - - - mV mV mV mV mV mV mV -3 60.5 0.5 - - - dB dB dB
Programmable gain amplifier input voltage (RMS value)
2002 May 16
24
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
SYMBOL (THD + N)/S PARAMETER total harmonic distortion-plus-noise to signal ratio CONDITIONS at -60 dB; A-weighted -3 dB setting 0 dB setting 3 dB setting 9 dB setting 15 dB setting 27 dB setting Digital-to-analog converter Vo(rms) output voltage (RMS value) note 3 unbalance between channels total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 100 mV 0 dB -60 dB; A-weighted code = 0; A-weighted - - - - - - - 900 0.1 -91 -40 100 100 50 - - - - - - tbf -37 tbf tbf tbf tbf MIN. TYP.
UDA1341TS
MAX. - - - - - - - - -86 - - - -
UNIT dB dB dB dB dB dB
mV dB dB dB dB dB dB
Vo
(THD + N)/S
S/N
cs
PSRR Notes
1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 k is used in series with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS). 2. The ADC input signal scales inversely proportional with the power supply voltage. 3. The DAC output voltage scales linear with the DAC analog supply voltage.
2002 May 16
25
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
UDA1341TS
12 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.7 to 3.6 V; Tamb = -20 to +85 C; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock timing (see Fig.8) Tsys clock cycle time fsys = 256fs fsys = 384fs fsys = 512fs tCWL tCWH LOW-level pulse width HIGH-level pulse width fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Serial input/output data timing (see Fig.9) Tcy tBCK(H) tBCK(L) tr tf ts;DATI th;DATI td;DATO(BCK) td;DATO(WS) th;DATO ts;WS th;WS Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tsu(L3)DA th(L3)DA tstp(L3) bit clock cycle time bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time data output delay time (from BCK falling edge) data output delay time (from WS edge) data output hold time word select set-up time word select hold time MSB-justified format 300 100 100 - - 20 0 - - 0 20 10 - - - - - - - - - - - - - - - - - - - - - - - - - 20 20 - - 80 80 - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns 78 52 39 0.30Tsys 0.40Tsys 0.30Tsys 0.40Tsys 88 59 44 - - - - 131 87 66 0.70Tsys 0.60Tsys 0.70Tsys 0.60Tsys ns ns ns ns ns ns ns
Microcontroller L3-interface timing (see Figs 5 and 6) L3CLOCK L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time L3MODE hold time L3MODE set-up time L3MODE hold time L3DATA set-up time L3DATA hold time L3MODE halt time addressing mode addressing mode data transfer mode data transfer mode data transfer and addressing mode data transfer and addressing mode 500 250 250 190 190 190 190 190 30 190 ns ns ns ns ns ns ns ns ns ns
2002 May 16
26
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
UDA1341TS
handbook, full pagewidth
tCWH
tCWL Tsys
MGL443
Fig.8 System clock timing.
handbook, full pagewidth
WS tBCK(H) td(DATO)(BCK)
tr BCK
tf
th;WS
ts;WS
tBCK(L) Tcy DATAO
td(DATO)(WS)
th;DATO
ts;DATI DATAI
th;DATI
MGG840
Fig.9 Serial interface timing.
2002 May 16
27
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
13 APPLICATION INFORMATION
UDA1341TS
handbook, full pagewidth L1 +3 V BLM32A07
L2 BLM32A07 ground C12 100 F (16 V)
VDDA VDDD C11 100 F (16 V)
VDDA R21 1
VDDD R28 1
C2 100 F (16 V) C21 100 nF (63 V)
C9 100 F (16 V) C25 100 nF (63 V) VADCN 5 7 VADCP C29 100 nF (63 V) VSSD 11
VSSA(ADC) VDDA(ADC) system clock R30 47 DATAO BCK WS DATAI overflow flag C1 left line input right C6 left MIC input right 47 F (16 V) 47 F (16 V) C7 VINR2 8 47 F (16 V) VINL2 6 47 F (16 V) C4 VINR1 4 OVERFL SYSCLK 1 12 18 16 17 19 9 3
VDDD 10
28
Vref C22 100 nF (63 V) C3 47 F (16 V)
26 VINL1 2
VOUTL
C5 47 F (16 V)
R23 100 R22 10 k
left output
UDA1341TS
24 VOUTR C8 R26 100 R27 10 k right output
47 F (16 V)
23 L3MODE L3CLOCK L3DATA 13 14 15 27 VSSA(DAC) C27 100 nF (63 V) C10 100 F (16 V) 25 VDDA(DAC) 22 21 20
QMUTE AGCSTAT TEST2 TEST1
R29 1 VDDA
MGR433
Fig.10 Application diagram.
2002 May 16
28
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
14 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
UDA1341TS
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
2002 May 16
29
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
15 SOLDERING 15.1 Introduction to soldering surface mount packages
UDA1341TS
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 May 16
30
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
UDA1341TS
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 May 16
31
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
16 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
UDA1341TS
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 May 16
32
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
NOTES
UDA1341TS
2002 May 16
33
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
NOTES
UDA1341TS
2002 May 16
34
Philips Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD) home stereo and portable applications
NOTES
UDA1341TS
2002 May 16
35
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/04/pp36
Date of release: 2002
May 16
Document order number:
9397 750 09805

▲Up To Search▲

Price & Availability of UDA1341TS

	To Download UDA1341TS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .